ASML and TSMC Launch Industry Push to Supersize Chipmaking's Photomasks

ASML Holding and Taiwan Semiconductor Manufacturing Co. said on Monday they are launching an industry-wide initiative to move the chipmaking world's most advanced lithography machines onto a larger photomask, a shift the two companies said is needed to unlock the full benefit of a new generation of extreme ultraviolet equipment already being installed in factories from Arizona to Taiwan.

The announcement, made jointly by the Dutch equipment maker and the world's largest contract chipmaker in a press release posted to ASML's newsroom, comes just ahead of the SPIE Photomask Technology and EUV Lithography conference opening this week in Monterey, California, where mask makers, chipmakers and equipment suppliers gather annually to hash out the industry's toolmaking roadmap. TSMC's decision to formally back the larger mask format is notable because the company had been the most prominent holdout, and its participation is expected to push the rest of the supply chain to follow.

What was announced

The initiative targets a transition from the six-inch photomasks used in chip fabrication for decades to a new 12-inch standard, sized to match the larger silicon wafers that have been the industry norm since the early 2000s. The push is aimed specifically at High NA EUV lithography, the newest class of extreme ultraviolet scanners that ASML has been shipping to customers over the past two years and that Intel, Samsung and now TSMC are working to fold into production.

High NA machines use a more aggressive numerical aperture and an anamorphic optical design that shrinks a chip pattern by a different factor along each axis of the mask. That design choice, while enabling finer features, also shrinks the usable exposure field on today's six-inch masks. For circuits or processor tiles larger than that field — increasingly common in AI accelerators and other large chips — manufacturers must stitch together multiple exposures, a workaround that adds design rules, alignment steps and yield risk at the seam. A 12-inch mask, matched to the wafer size already in use, would restore a full exposure field and remove much of that complexity.

"When industry works together to solve complex problems, we unlock possibilities that no single company could achieve alone," TSMC chairman and chief executive C.C. Wei said in the companies' joint statement.

The timing was no accident: Intel Foundry and ASML used the same conference to disclose a related milestone, saying Intel had processed more than one million wafers using High NA EUV across tool certification, research and volume production, including select layers of its Core Ultra Series 3 "Panther Lake" chips. Intel has run High NA tools longer than any rival and has for three years pushed the industry toward the large-format mask, making Monday's ASML-TSMC announcement as much a validation of Intel's early bet as a new initiative.

ASML and TSMC laid out a staged rollout rather than an immediate switch. High NA EUV tools will continue running on six-inch masks for their first production use, with TSMC saying it plans to bring High NA lithography into high-volume manufacturing for advanced logic nodes starting in 2030. The companies are targeting a 12-inch mask pilot line by 2031, with production-ready 12-inch High NA systems expected to reach advanced-node manufacturing by 2033 — a runway of roughly seven years from Monday's announcement.

Samsung, which has said it aims to bring High NA EUV into memory production by 2028, and Intel, which has been running High NA tools in its Oregon development fabs longer than any rival, are both described in industry coverage as supporting the broader shift toward the larger mask, alongside mask blank and equipment suppliers that would need to retool to produce them. IDC analyst Andrew Buss, quoted in a technical analysis published by the semiconductor trade site SemiWiki, compared the scale of the undertaking to the industry's earlier move from 200-millimeter to 300-millimeter silicon wafers, a transition in the late 1990s and early 2000s that took the better part of a decade and reshaped supply chains across the sector.

• Six inches: the photomask size used in chip production since EUV lithography began, and still standard for early High NA use
• 12 inches: the new target mask size, matched to today's standard silicon wafer diameter
• 2030: when TSMC plans to begin high-volume manufacturing using High NA EUV
• 2031: target date for a pilot line producing 12-inch masks
• 2033: target date for 12-inch High NA systems to reach advanced-node production

Why chipmakers say it matters

The economic case rests on throughput. EUV scanners are among the most expensive machines in any fab, with High NA tools costing substantially more than their predecessors, and the industry has said the smaller exposure field on six-inch masks forces more stage movements and exposure steps per wafer, lowering the number of wafers a tool can process per hour. Spreading a scanner's cost and operating expense across more usable chips is central to keeping the price per transistor from rising as nodes shrink — a concern that has grown more acute as demand for AI accelerators pushes chip designers toward ever-larger die sizes that are especially prone to needing stitched exposures.

Christophe Fouquet, ASML's president and chief executive, framed the move as a natural next step for a technology still in its early deployment phase. "We expect the adoption of High NA EUV to increase progressively, first using current 6-inch masks and then further supported by 12-inch masks," Fouquet said in the companies' statement, adding that the larger format is intended to maximize the productivity gains High NA is designed to deliver.

Bringing a 12-inch mask to market is not simply a matter of scaling up existing parts. It requires new blanks, substrates, absorber materials, pattern-writing tools, inspection systems, handling robots and scanner interfaces, all built to the nanometer-level tolerances that EUV lithography demands — infrastructure that does not yet exist commercially at that size and that will need to be developed in parallel across dozens of supplier companies.

Who is affected

The shift touches nearly every layer of the chipmaking supply chain: the equipment makers that build EUV scanners and mask-writing tools, the specialty glass and materials suppliers that produce mask blanks, the handful of mask shops that pattern and inspect finished photomasks, and the chip designers at companies building AI processors, advanced smartphone chips and other leading-edge silicon who stand to benefit from fewer stitching constraints. TSMC, which trades on the New York Stock Exchange as an American depositary receipt and discloses its manufacturing plans to U.S. investors through periodic reports filed with the Securities and Exchange Commission, counts most of the world's largest fabless chip designers as customers, and those customers will ultimately see the effects of the mask transition in cost and yield on future advanced-node products, though not until the 2030s given the timeline laid out Monday.

Toolmakers and mask suppliers that had been waiting for clearer industry consensus before committing capital to 12-inch mask infrastructure are likely to move first, since a multiyear pilot line effort requires investment well ahead of any production payoff. Because the transition is explicitly industry-wide rather than proprietary to any one company, ASML and TSMC said other equipment makers, mask suppliers and manufacturers are being invited to join the effort as it moves from announcement to execution.

What happens next

The near-term marker will be TSMC's 2030 target for bringing High NA EUV into high-volume production on existing six-inch masks — a milestone that will show whether the newest lithography tools perform as expected at commercial scale before the industry attempts the more disruptive move to a new mask format. Progress toward the 2031 pilot line will likely surface in technical papers and supplier announcements at future SPIE photomask gatherings, the same venue where this week's announcement was timed to land, as mask blank producers, inspection-tool makers and materials suppliers report on their own development work.

Whether the 2033 production target holds will depend on how quickly that broader ecosystem — glass suppliers, pattern generators, metrology firms — can qualify 12-inch parts to the tolerances EUV lithography requires. Trade coverage of the announcement, including a report from The Register, noted that the industry has set precise-sounding dates before without always meeting them, and that the roughly decade-long precedent set by the last major wafer-size transition leaves substantial room for delay before 12-inch masks reach production chips.